1. Field of the Invention
The present invention relates to a method of manufacturing light-receiving or emitting diode array chips. The term light-receiving or emitting diode is used to cover both a light emitting diode and a light-receiving diode.
2. Description of Prior Art
Light-emitting diode arrays are usually used as a light source for use in, for example, electrophotographic printers. This type of light-emitting diode array is manufactured by arranging a plurality of light-emitting diode array chips (referred to as chip hereinafter) in line on a printed circuit board. For example, Japanese Utility Model (KOKAI) No. 2-8067 discloses a method of manufacturing the chips.
According to the method, a semiconductor substrate of a first conductivity type has an interlayer dielectric thereon formed in each of a plurality of areas. The interlayer dielectric is formed with a plurality of windows therein. The plurality of areas will be separated into individual chips at a later stage of the manufacturing process. The windows are arranged in array form at predetermined intervals. The interlayer dielectric is used as a diffusion mask so as to form impurity diffusion areas of a second conductivity type in the substrate. Then, an electrode is formed on the interlayer dielectric for each impurity diffusion area. Then, the substrate having the electrodes (referred to as wafer hereinafter) formed thereon is cut into individual chips. The contour of the interlayer dielectric is used as a positioning mark for a separator (typically, a dicing blade) during the separation stage, allowing high precision separation. A single interlayer dielectric may have some pin holes therein which cause the individual electrodes to be electrically short-circuited to the substrate. In order to prevent this type of short-circuit, it is common practice to form a second interlayer dielectric on a first interlayer dielectric.
A plurality of chips are arranged side by side on a printed circuit board in order to make a long line of light-receiving/emitting elements. If the light-receiving elements or light-emitting elements in each chip are arranged at predetermined intervals of P, then each chip after the dicing process must have a dimensional margin of less than P/2 at the extremities of the aligned light-receiving/emitting elements. This is necessary in order to arrange adjacent chips on the circuit board such that the distance between the last light-emitting elements on the adjacent chips is equal to the interval P.
The higher resolution the light-receiving diode array or light-emitting diode array is to have, the smaller the interval P must be. Accordingly, the chips need to have as small a dimensional margin at longitudinal ends thereof as possible.
As the dimensional margin at the ends of the chip is made smaller, there will be a greater chance that the dicing blade will cut parts of the interlayer dielectric. This gives rise to a problem that the interlayer tends to become detached from the substrate. This problem will be described in more detail with reference to FIGS. 11-13.
FIG. 11 is a top view of the prior art wafer disclosed in the aforementioned KOKAI No. 2-8067, showing some of the relevant areas which will be separated into individual chips at a later stage of the manufacturing process. FIGS. 12 and 13 are enlarged cross-sectional views taken along lines I--I of an area indicated by Y. Electrodes are not shown for simplicity of explanation. FIG. 13 shows a cross-sectional view when the impurity diffusion area of the last light-emitting element 15a reaches an unused impurity diffusion area.
The interlayer dielectric 13 is formed on the substrate 11 of the first conductivity type and has windows 14a formed therein. A positioning mark 17 is formed at an edge line of the interlayer dielectric 13 and is used for positioning of a dicing blade 23. An unused impurity diffusion area 19 of the second conductivity type is formed adjacent the positioning mark 17 (edge line of the interlayer dielectric 13), next to the last impurity diffusion area 15. The individual electrodes are depicted at 21.
In order to cut the wafer into individual chips, a dicing operation is performed both in the longitudinal direction (horizontal direction in FIG. 11) and in the lateral direction (vertical direction in FIG. 11). A high precision dicing is required when cutting the wafer in the lateral direction because the blade position relative to the light-emitting elements directly dictates the dimensional margin at the longitudinal ends of the individual chips after dicing.
Thus, the following description is focused on the dicing operation performed in the lateral direction.
As described previously, when cutting the wafer in the lateral direction, the chips must have a dimensional margin less than P/2 at their longitudinal ends as shown in FIGS. 12 and 13 after the wafer has been cut. Thus, the dicing blade 23 is positioned with respect to the wafer using the positioning mark 17 so as to meet the following conditions. That is, the width W of the interlayer dielectric 13 formed on the chip is less than P/2. The edge line of the interlayer dielectric is used as the positioning mark 17. However, it is to be noted that the smaller P is made in an attempt to implement a high resolution light-receiving diode array or a light-emitting diode array, the narrower the width W of the interlayer dielectric becomes. Thus, as shown in FIG. 13, the unwanted, unused impurity diffusion areas 19 will become continuous with the impurity diffusion area 15 which is used as a last light-emitting element. This unwanted continuity of impurity diffusion areas gives rise to another problem.
If the interlayer dielectric serves as a diffusion mask, the interlayer dielectric must have a certain width W at the chip ends. However, as mentioned above, the chips must have a dimensional margin less than P/2 at their longitudinal ends. Thus, the dicing blade 23 cuts the interlayer dielectric 13, increasing the chance of the interlayer dielectric near the chip ends becoming detached from the substrate. If the interlayer dielectric includes a first interlayer dielectric and a second interlayer dielectric, a problem frequently occurs that the second interlayer dielectric becomes detached from the first interlayer dielectric.
If the interlayer dielectric becomes detached from the first interlayer dielectric near the impurity diffusion area 15, the light-emitting element closest to the interlayer dielectric emits light of a different power from other light-emitting portions. This causes poor print quality of the printer. If the detachment of the interlayer dielectric spreads to the individual electrodes 21, the individual electrodes 21 are short-circuited to the substrate 11.